Method for producing a vertical MOS-transistor

ABSTRACT

In order to produce a vertical MOS transistor with optimized gate overlap capacitances, a mesa structure is formed with an upper source/drain region, a channel region and a lower source/drain region. With the aid of chemical/mechanical polishing, an insulation structure is formed which essentially covers the side walls of the lower source/drain region. A gate dielectric and a gate electrode, whose height is essentially equal to the height of the channel region, are formed on the side walls of the channel region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to a method for the production of avertical MOS transistor.

2. Discussion of the Related Art

With a view to ever-faster components with higher integration density,the structural sizes of integrated circuits are decreasing fromgeneration to generation. This is also true with regard to CMOStechnology. It is generally expected (see, for example, Roadmap ofSemiconductor Technology, Solid State Technology 3, 1995), that MOStransistors with a gate length of less than 100 nm will be used aroundthe year 2010.

On the one hand, attempts have been made to scale modern CMOS technologyin order to produce planar MOS transistors with such gate lengths (see,for example, A. Hori, H. Nakaoka, H. Umimoto, K. Yamashita, M. Takase,N. Shimizu, B. Mizuno, S. Odanaka, A 0.05 μm-CMOS with Ultra ShallowSource/Drain Junctions Fabricated by 5 keV Ion Implantation and RapidThermal Annealing, IEDM 1994, 485 and H. Hu, L. T. Su, Y. Yang, D. A.Antoniadis, H I. Smith, Channel and Source/Drain Engineering inHigh-Performance sub-0.1 μm NMOSFETs using X-ray lithography, Symp. VLSITechnology, 17, 1994). The production of such planar MOS transistorswith a channel length of less than 100 nm requires the use of electronbeam lithography and has hitherto been possible only on a laboratoryscale. The use of the electron beam lithography leads to asuperproportional increase in development costs.

In parallel with this, vertical transistors have been investigated witha view to producing shorter channel lengths (see L. Risch, W. H.Krautschneider, F. Hofmann, H. Schäfer, Vertical MOS Transistor with 70nm channel length, ESSDERC 1995, pages 101 to 104). In this case, layersequences are formed corresponding to the source, channel and drain, andare annularly surrounded by the gate dielectric and gate electrode. Interms of their radio-frequency and logic properties, these vertical MOStransistors have to date been unsatisfactory in comparison with planarMOS transistors.

German patent no. 196 21 244 has proposed a MOS transistor with reducedstray gate capacitances, which is suitable for radio-frequencyapplications. In order to produce this vertical transistor, a mesastructure comprising a source region, channel region and drain region invertical succession is formed on a semiconductor substrate. The gateelectrode is formed in such a way that it adjoins the mesa structureonly at the channel region. Oxide structures, which embed the gateelectrode, are formed below and above the gate electrode at the sourceand drain regions. The gate capacitances are minimized in this way. Inorder to produce the oxide structures and the gate electrode,corresponding layers are respectively deposited which cover the mesa.Photoresist is applied on top and planarized. The photoresist issubsequently etched back to an extent that leaves free the upper sidesof the mesa. This structured photoresist is subsequently used as a maskin order to structure the underlying layer at the mesa. The thickness ofthe layer is in each case less than the height of the mesa. Since theplanarity is limited by the flow of planarized photoresist, the heightof the etching erosion in the further structuring of the photoresistlayer by etching is difficult to control.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a method for the productionof a vertical MOS transistor with reduced gate overlap capacitances,which is essentially improved with regard to process reliability.

This object is achieved in accordance with the invention in a method forproducing a vertical MOS transistor having a mesa structure, which has alower source/drain region, a channel region and an upper source/drainregion, is formed from a semiconductor layer sequence. The semiconductorlayer sequence is formed by epitaxy or by implantation and annealing. Afirst auxiliary layer, which is structured together with thesemiconductor layer sequence, is applied to the semiconductor layersequence. A terminal region for the lower source/drain region is formedlaterally with respect to the mesa structure in the semiconductorsubstrate. An insulation structure is formed which essentially covers atleast the side wall of the lower source/drain region. A gate dielectricand a gate electrode are formed on the side of the channel region. Theheight of the gate electrode is essentially equal to the height of thechannel region. In order to form the insulation structure, an insulatinglayer is applied whose thickness is greater than or equal to thethickness of the semiconductor layer sequence. The insulating layer isplanarized by chemical/mechanical polishing. In this case, the firstauxiliary layer, which is located as the uppermost layer on the mesastructure, is used as an etching stop.

A flat zone, in which the surface of the first auxiliary layer isexposed, is formed by the chemical/mechanical polishing. This provides areference plane for subsequent etching steps. The depth of the etchingerosion in subsequent etching steps can therefore be controlled betterthan in the prior art.

According to one embodiment of the invention, the insulating layer isapplied with essentially conformal edge coverage. Its thickness in thiscase is essentially equal to the thickness of the semiconductor layersequence. This means that, laterally with respect to the mesa structure,the surface of the insulating layer is level with the surface of theupper source/drain region of the mesa structure.

A second auxiliary layer is applied which has the same etchingproperties and essentially the same thickness as the first auxiliarylayer. Laterally with respect to the mesa structure, the surface of thesecond auxiliary layer is therefore arranged level with the surface ofthe first auxiliary layer. The second auxiliary layer is subsequentlystructured in such a way that the surface of the insulating layer isexposed at least in a first area, The first area laterally overlaps themesa structure. The lateral dimensions of the first area arerespectively greater by at least twice the layer thickness of theinsulating layer than corresponds to the corresponding lateral dimensionof the mesa structure. The second auxiliary layer therefore covers theinsulating layer in the part which is arranged outside the mesastructure and in which the elevation of the mesa structure does not havean effect on the topology of the insulating layer. In other words:during the structuring of the second auxiliary layer, that part of thesecond auxiliary layer is removed in which the surface of the secondauxiliary layer is arranged above the surface of the first auxiliarylayer. After the structuring of the second auxiliary layer, the surfaceof the first auxiliary layer and the surface of the second auxiliarylayer are arranged everywhere at the same level.

The surface of the first auxiliary layer is subsequently exposed bychemical/mechanical polishing of the insulating layer. The firstauxiliary layer and the second auxiliary layer in this case act as anetching stop.

Subsequently, using the first auxiliary layer and the second auxiliarylayer as a mask, the insulating layer is etched to such an extent thatthe side wall of the channel region is essentially exposed. Theinsulating layer is not etched underneath the channel region, so that,on the side wall of the mesa structure, the insulating layer extends asfar as the boundary between the lower source/drain region and thechannel region.

A gate dielectric is formed on the exposed side wall of the channelregion.

A conductive layer is produced which essentially fills the intermediatespace between the insulating layer and the mesa structure. Theintermediate space between the insulating layer and the mesa structureis produced by the etching of the insulating layer as far as the upperboundary of the lower source/drain region. The gate electrode issubsequently formed by etching back the conductive layer.

The second auxiliary layer is preferably structured in such a way thatthe surface of the insulating layer is additionally exposed in a secondarea. During the etching of the insulating layer to expose the side wallof the channel region, the insulating layer is also etched in the secondarea, so that a continuous opening is produced in the second area and inthe first area. During the formation of the conductive layer, thisopening is essentially filled. The gate electrode formed by etching backthe conductive layer therefore has the cross-section of the opening. Inthe subsequent course of the process, a contact hole for the gateelectrode is opened in the second area.

It is particularly advantageous, during the structuring of the secondauxiliary layer, to provide auxiliary structures in the second areawhich, during the structuring of the insulating layer, make islands fromthe material of the insulating layer in the opening. In the second area,the opening and therefore the gate electrode has a grid-shapedcross-section. A thickness of the conductive layer corresponding to thedimensions of the opening is then sufficient for filling the openingwith the conductive layer. Furthermore, the grid-shaped cross-section ofthe gate electrode in the second area has the advantage that alignmentis not critical when opening the contact hole to the gate electrode. Theislands are preferably arranged in such a way that the distance betweenislands which lie opposite one another in the second area is not greaterthan the distance between the side wall of the mesa structure and theopposite side wall of the insulating structure in the first area. Thisreduces the required thickness of the conductive layer.

It is within the scope of the invention to apply a third auxiliary layerbefore removing the first auxiliary layer and the second auxiliarylayer. The first auxiliary layer and the second auxiliary layer can beetched selectively with respect to the third auxiliary layer. The thirdauxiliary layer is structured in such a way that the first auxiliarylayer is exposed and the second area is covered by the third auxiliarylayer. The effect achieved by this is that the first auxiliary layer,which is arranged on the surface of the mesa structure, can be removedwhile the second auxiliary layer remains in the second area on thesurface of the silicon islands. The effect of this is that, duringfabrication of the structure, contact holes to the terminal regions ofthe lower source/drain region and contact holes to the gate electrodecan be etched separately. This avoids etching through the insulatinglayer at the islands in the second area, which can lead toshort-circuits between the semiconductor substrate and the gateelectrode.

It is within the scope of the invention for the first auxiliary layerand the second auxiliary layer to contain Si₃N₄ and for the thirdauxiliary layer, if present, to contain polysilicon. The insulatinglayer and the insulating filling contain SiO₂. The conductive layercontains doped polysilicon, metal silicide, metal and/or a combinationof these materials. Suitable materials for the conductive layer are,however, ones which are appropriate for gate electrodes.

In another embodiment of the invention, the insulating layer is erodedby chemical/mechanical polishing as far as the level of the firstauxiliary layer. It is subsequently structured by etching it back, withthe insulation structure which is arranged laterally with respect to themesa structure and whose thickness is essentially equal to the height ofthe lower source/drain region being formed. The side wall of the channelregion is in this case likewise exposed. A gate dielectric is formed onthe side wall of the channel region. A conductive layer is deposited andstructured in order to form the gate electrode. In this case, parts ofthe conductive layer which are arranged on the side walls of the mesaabove the channel region, or on the surface of the mesa, are removed. Afurther insulating layer is applied which covers the gate electrode.

It is within the scope of the invention for the insulating layer, thefurther insulating layer and/or the insulating filling to contain SiO₂,and for the first auxiliary layer to contain silicon nitride. Allmaterials which are customary as a gate electrode material are suitablefor the conductive layer, in particular doped polysilicon, metalsilicide, metal and/or a combination of these materials.

These and other objects of the invention will become clearer withreference to the following detailed description of the preferredembodiments and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side view of a semiconductor substrate with a semiconductorlayer sequence and a first auxiliary layer;

FIG. 2 is a cross-section through the semiconductor substrate after theformation of a mesa structure by structuring the semiconductor layersequence, after the formation of spacers on the side walls of the mesastructure, and after the formation of a terminal region;

FIG. 3 is a cross-section through the semiconductor substrate after theapplication of an insulating layer and after the application andstructuring of a second auxiliary layer;

FIG. 4 is a plan view of FIG. 3;

FIG. 5 is a cross-section through the semiconductor substrate after theinsulating layer has been planarized;

FIG. 6 is a cross-section through the semiconductor substrate afterpartial exposure of the side wall of the mesa structure and theformation of a gate dielectric on the exposed side wall of the mesastructure;

FIG. 7 is a cross-section through the semiconductor substrate after theformation of a gate electrode;

FIG. 8 is a cross-section through the semiconductor substrate after theformation of a metal silicide layer on the surface of the gateelectrode, after the formation of insulating filling which lies abovethe gate electrode and ends level with the first and second auxiliarylayers, and after the deposition and structuring of a third auxiliarylayer;

FIG. 9 is a cross-section through the semiconductor substrate after theformation of contacts;

FIG. 10 is a cross-section through a semiconductor substrate with a mesastructure which has a first auxiliary layer as the uppermost layer andwith a terminal region in the semiconductor substrate;

FIG. 11 is a cross-section through the semiconductor substrate after theformation of metal silicide layers on the surface of the terminal regionand after the formation of an insulating layer which is deposited to agreater thickness than the mesa structure and the first auxiliary layerand which is subsequently planarized;

FIG. 12 is a cross-section through the semiconductor substrate after theinsulating layer has been etched back and after the formation of a gatedielectric on the side walls of the mesa structure;

FIG. 13 is a cross-section through the semiconductor substrate after theformation of a further insulating layer whose thickness is greater thancorresponds to the height of the exposed mesa structure, and planarizingof the further insulating layer;

FIG. 14 is a cross-section through the semiconductor substrate after theinsulating layer has been etched back; and

FIG. 15 is a cross-section through the semiconductor substrate after thefirst auxiliary layer has been removed, after the formation of a metalsilicide layer on the exposed surface of the mesa structure and afterthe formation of contacts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, a first silicon layer 2, a second silicon layer 3and a third silicon layer 4 are applied to a substrate 1, for example amonocrystalline silicon wafer or the monocrystalline silicon layer of anSOI substrate. The first silicon layer 2, the second silicon layer 3 andthe third silicon layer 4 are in this case respectively formed by insitu doped epitaxy using a process gas containing Si₂H₂Cl₂, B₂H₆, AsH₃,PH₃, HCl, H₂ in the temperature range of from 700° C. to 950° C. and inthe pressure range of from 100 to 10,000 Pa. The first silicon layer 2is formed to a thickness of 200 nm from n-doped silicon with a dopantconcentration of 5×10¹⁹ cm⁻³. The second silicon layer 3 is formed to athickness of 100 nm from p-doped silicon with a dopant concentration of10¹⁸ cm⁻³. The third silicon layer 4 is formed to a thickness of 100 nmfrom n-doped silicon with a dopant concentration of 5×10¹⁹ cm⁻³. Arsenicor phosphorus are used as the dopant for n-doped silicon, and boron isused as the dopant for p-doped silicon.

A first auxiliary layer 5 is applied to the third silicon layer 4. Thefirst auxiliary layer 5 is formed from silicon nitride in a thickness of200 nm.

Referring to FIG. 2, using photolithographic process steps, the firstauxiliary layer 5, the third silicon layer 4, the second silicon layer 3and the first silicon layer 2 are subsequently structured by anisotropicdry etching, for example with CHF₃, O₂ (for nitride) or HBr, NF₃,Heinonen, O₂ (for silicon). In this case, a mesa structure 6 is formed.During the structuring, use is made of lithography with a minimumlithographic dimension of F=0.6 μm and a maximum misalignment of 0.2 μm.The etching is continued about 100 nm into the substrate 1, so that thefirst silicon layer 2 is also removed outside the mesa structure 6. Themesa structure 6 has a cross-section of F×F parallel to the surface ofthe substrate 1.

During the formation of the mesa structure 6, a lower source/drainregion 2′ is formed from the first silicon layer 2, a channel region 3′is formed from the second silicon layer 3 and an upper source/drainregion 4′ is formed from the third silicon layer 4.

The side walls of the mesa structure 6 are subsequently provided with a50 nm thick SiO₂ spacer 7. By implantation, for example with arsenic ata dose of 5×10¹⁵ cm⁻², and an energy of 40 keV, a terminal region 8which annularly surrounds the mesa structure is formed laterally withrespect to the mesa structure 6 in the semiconductor substrate 1.

Referring to FIG. 3, after the SiO₂ spacers 7 have been removed, aninsulating layer 9 of SiO₂ is applied surface-wide with essentiallyconformal edge coverage. The insulating layer 9 is formed in a thicknesswhich corresponds to the height of the mesa structure 6, which comprisesthe lower source/drain region 2′, the channel region 3′ and the uppersource/drain region 4′. The thickness of the insulating layer 9 istherefore, for example, 500 nm.

A second auxiliary layer 10 of Si₃N₄ is subsequently applied andstructured selectively with respect to SiO₂. The second auxiliary layer10 has essentially the same thickness as the first auxiliary layer 5,that is to say, for example, 200 nm. The second auxiliary layer 10 isstructured in such a way that a surface of the insulating layer 9 isexposed in a first area 11, which laterally overlaps the mesa structure6 and whose lateral dimensions are greater by at least twice the layerthickness of the insulating layer 9 than the corresponding lateraldimension of the mesa structure 6. The surface of the insulating layer 9is furthermore exposed in a second area 12, which adjoins the first area11 In the second area 12, island-like parts of the second auxiliarylayer 10 remain during the structuring of the second auxiliary layer 10(see FIG. 3 and the plan view of FIG. 3 which is represented in FIG. 4,the first area 11 and the second area 12 being respectively shown as adouble arrow with the corresponding reference number). The sectionthrough FIG. 4 which is represented in FIG. 3 is denoted III—III in FIG.4. The region where the topology of the insulating layer 9 has changedon account of the mesa structure 6 arranged underneath is indicated as adashed line in FIG. 4. Furthermore, the cross-section of the mesastructure 6, which cannot be seen in the plan view, has been indicatedas a dashed line.

Referring to FIG. 5, the insulating layer 9 is subsequently planarizedby chemical/mechanical polishing. In this case, those parts of theinsulating layer 9 which are arranged above the first auxiliary layer 5are removed. The first auxiliary layer 5 and the second auxiliary layer10 of silicon nitride act in this case as an etching stop. For thisreason, the erosion of the insulating layer 9 stops as soon as thesurface of the first auxiliary layer 5 or of the second auxiliary layer10 is reached. Gaps remaining between the parts of the second auxiliarylayer 10 and the insulating layer 9 are subsequently filled by conformaldeposition and structuring of an SiO₂ layer with an insulating filling13.

Referring to FIG. 6, using the first auxiliary layer S and the secondauxiliary layer 10 as etching mask, the insulating layer 9 and theinsulating filling 13 are subsequently etched. The etching is carriedout, for example, with C₄F₈ selectively with respect to silicon nitride.In this case, the depth of the etching is determined through the etchingtime. The insulating layer 9 is etched to such an extent that the sidewalls of the upper source/drain region 4′ and of the channel region 3′are exposed. Conversely, the side walls of the lower source/drain region2′ remain covered by the insulating layer 9. A gate dielectric 14 of,for example SiO₂, is then formed in a layer thickness of, for example, 5nm by thermal oxidation on the exposed side walls of the channel region3′ and of the upper source/drain region 4′.

Referring to FIG. 7, in the opening resulting from the etching of theinsulating layer 9, a gate electrode 15 is substantially formed bydepositing a, for example, 400 nm thick n-doped polysilicon layer andsubsequent planarizing with the aid of chemical/mechanical polishing andanisotropically etching back the polysilicon layer with HBr, Cl₂,Heinonen, O₂. The gate electrode 15 covers the entire bottom of theaforementioned opening. It has a height corresponding to the height ofthe channel region 3′, for example 100 nm.

During the planarizing of the doped polysilicon layer, the firstauxiliary layer 5 and the second auxiliary layer 10, each of whichcontain silicon nitride, again serve as a defined etching stop It istherefore possible to set the height of the gate electrode 15 accuratelyto a thickness corresponding to the channel length, for example 100 nm,by means of the duration of the anisotropic etching.

Insulating spacers 16, for example of SiO₂, are subsequently formed onthe flanks of the opening in which the gate electrode 15 was formed. Theinsulating spacers 16 are formed by conformly depositing a 50 nm thickSiO₂ layer and subsequently etching back anisotropically selectivelywith respect to silicon and silicon nitride, for example with CHF₃, O₂.

Referring to FIG. 8, the gate electrode 15 is subsequently provided witha silicide terminal 17 by self-aligned siliciding. This is done, forexample, by surface-wide application of a titanium layer which, in asubsequent heat-treatment step, forms the silicide terminal 17 with theunderlying silicon of the gate electrode 15. In contrast, the titaniumdoes not react with silicon nitride or silicon oxide, so that it can besubsequently removed selectively with respect to the silicide terminal17.

The area above the silicide terminal 17 between the insulating spacers16 is subsequently provided with an insulating filling 18, for exampleof SiO₂. The insulating filling 18 ends level with the first auxiliarylayer 5 and the second auxiliary layer 10. In order to form theinsulating filling 18, a further insulating layer is depositedsurface-wide in a thickness of, for example, 300 nm. By planarizing bymeans of chemical/mechanical polishing, the insulating filling 18 isformed therefrom. The first auxiliary layer 5 and the second auxiliarylayer 10 again act as an etching stop.

A third auxiliary layer 19, for example of polysilicon, is applied in athickness of 100 nm and structured in such a way that the thirdauxiliary layer 19 covers the second auxiliary layer 10 in the secondarea 12 (see FIG. 4 and FIG. 8).

Referring to FIG. 9, the first auxiliary layer 5 and the secondauxiliary layer 10, unless covered by the third auxiliary layer 19, aresubsequently removed selectively with respect to SiO₂and silicon, forexample with hot H₃PO₂. In this case, the surface of the uppersource/drain region 4′ is exposed. In other words, a contact is openedto the upper source/drain region 4′ with self-alignment.

After the third auxiliary layer 19 has been removed, photolithographicprocess steps are used to open contact holes to the terminal region 8and to the silicide terminal 17 of the gate electrode 15. Contacts 20are formed to the terminal region 8, the upper source/drain region 4′and the terminal region 17 of the gate electrode 15 by forming andstructuring a metal layer, preferably of Al Si (1 percent) Cu (0.5percent). During the opening of the contact hole to the silicideterminal 17 of the gate electrode 15, the part of the second auxiliarylayer 10 remaining in the second area prevents the part of theinsulating layer 9 arranged under the islands of the second auxiliarylayer 10 from being etched through. Since this part of the insulatinglayer 9 has the same thickness as the insulating layer 9 in the areawhere the contact hole is formed to the terminal region 8, ashort-circuit between the gate electrode 15 and the terminal region 8 isthereby avoided. The provision of islands in the region of the contact20 to the gate electrode 15 makes it possible to have a fairly largecontact hole, even if the dimensions of the mesa structure 6 (see, FIG.6) and the islands are close to the minimum lithographic dimension F.The cross-section of the contact to the gate electrode 15 can thereforebe optimized in terms of its electrical properties.

If the process is carried out so accurately that there is no risk of ashort-circuit between the gate electrode 15 and the terminal region 8,the use of the third auxiliary layer 19, which protects the secondauxiliary layer 10 at the contact to the gate electrode 15, may beobviated.

Referring to FIG. 10, in a further illustrative embodiment, a mesastructure 22, which comprises a lower source/drain region 23, a channelregion 24 and an upper source/drain region 25 in vertical succession, isformed on a substrate 21, for example a monocrystalline silicon wafer orthe monocrystalline silicon layer of an SOI substrate. The lowersource/drain region 23 consists of n-doped silicon with a dopantconcentration of 5×10¹⁹ cm⁻³ and a thickness of 100 nm. The channelregion 24 consists of p-doped silicon with a dopant concentration of10¹⁸ cm⁻³ and a thickness of 100 nm. The upper source/drain region 25consists of n-doped silicon with a dopant concentration of 5×10¹⁹ cm⁻³and a thickness of 200 nm. Arsenic or phosphorous are used as the dopantfor n-doped silicon, and boron is used as the dopant for p-dopedsilicon.

In order to form the mesa structure 22, a semiconductor layer sequencewith an n-doped first silicon layer, a p-doped second silicon layer andan n-doped third silicon layer is grown by epitaxy with Si₂H₂Cl₂, B₂H₆,AsH₃, PH₃, HCl, H₂, as in the first illustrative embodiment. As analternative, the semiconductor layer sequence may be formed byimplantation and annealing. After application of an auxiliary layer 26,the layer sequence and the auxiliary layer 26 are structured byanisotropic etching to form the mesa structure 22. The mesa structure 22is formed with an essentially square cross-section having a side lengthof 0.6 μm. The lithography which is used has in this case a minimumlithographic dimension of F=0.6 μm and a misalignment of at most 0.2 μm.

The anisotropic etching to form the mesa structure 22 is continued untilthe third silicon layer is also sure to have been penetrated during theformation of the lower source/drain region 23. The anisotropic etchingis, for example, carried out with CHF₃, O₂ (for nitride) or HBr, NF₃,Heinonen, O₂ (for silicon).

The flanks of the mesa structure 22 are subsequently provided with SiO₂spacers 27. The SiO₂ spacers 27 are, for example, formed by depositingan SiO₂ layer in a thickness of 50 nm and subsequently etching backanisotropically. In order to form a terminal region 28 for the lowersource/drain region 23, implantation with arsenic at 40 keV and 5×10¹⁵cm⁻² is subsequently carried out. The dopant is activated by aheat-treatment at, for example, 1000° C. for 10 seconds.

Referring to FIG. 11, a silicide terminal 29 is then formed on thesurface of the terminal region 28 by self-aligned silicide formation.The silicide terminal 29 is, for example, formed from TiSi₂. It is usedto reduce the series resistance of the terminal region 28 and the lowersource/drain region 23. The terminal region 28 annularly surrounds themesa structure 22.

An insulating layer 30, whose thickness is greater than the combinedheight of the mesa structure 22 and the auxiliary layer 26, issubsequently applied surface-wide. The insulating layer 30 has, forexample, a thickness of 600 nm. The insulating layer 30 is planarized bychemical/mechanical polishing. In this case, the auxiliary layer 26 madeof silicon nitride acts as an etching stop.

Referring to FIG. 12, the insulating layer 30 is etched, selectivelywith respect to nitride, to an extent which produces an insulationstructure 31 ending level with the top of the lower source/drain region23. This etching is, for example, carried out wet-chemically with NHF₄,HF. Since, after the planarizing, the insulating layer 30 ends levelwith the auxiliary layer 26 and has been planarized bychemical/mechanical polishing, the depth of the etching during theformation of the insulation structure 31 can be controlled accuratelythrough the etching time In this case, the flanks of the channel region24 and of the upper source/drain region 25 are exposed.

A gate dielectric 32, which has a thickness of, for example, 5 nm, issubsequently formed on the flanks of the channel region 24 and of theupper source/drain region 25 by thermal oxidation.

Referring to FIG. 13, a doped polysilicon layer 33 is then produced. Thedoped polysilicon layer 33 has a thickness which corresponds at least tothe sum of the thicknesses of the channel region 24, of the uppersource/drain region 25 and of the auxiliary layer 26. This means thatthe doped polysilicon layer 33 has a thickness of, for example, 500 nm.The doped polysilicon layer 33 is planarized by chemical/mechanicalpolishing. In this case, the auxiliary layer 26 acts as an etching stop.The doped polysilicon layer 33 is etched back by etching with HBr, Cl₂,Heinonen, O₂, selectively with respect to silicon nitride and siliconoxide. In this case, a gate electrode layer 33′ is formed whose heightcorresponds to the height of the channel region 24. This means that thegate electrode layer 33′ has a height of 100 nm (see FIG. 14).

Referring to FIG. 15, using photolithographic process steps, the gateelectrode layer 33′ is structured, a laterally bounded gate electrode33′ being formed. According to the alignment of the photoresist maskused in this case, the gate electrode 33″ then annularly surrounds themesa structure 22 (FIG. 11) or is arranged only along some of the flanksof the mesa structure 22 (FIG. 11). By means of such overlap between thephotoresist mask and the mesa structure 22, it is possible to reduce thewidth of the transistor to less than the minimum structure size F.

The gate electrode 33″ is covered with a further insulation structure34. To form the further insulation structure 34, a further insulationlayer of, for example, SiO₂ is formed which projects over the mesastructure 22 (FIG. 11 )and the auxiliary layer 26. The furtherinsulation structure 34 is formed by planarizing and etching back thefurther insulation layer. The auxiliary layer 26 is subsequently removedselectively with respect to SiO₂ and silicon, for example with hotH₃PO₄. In this case, the surface of the upper source/drain region 25 isexposed. The exposed surface of the upper source/drain region 25 isprovided with a silicide terminal region 35 of, for example, TiSi₂. Thesilicide terminal region 35 is, for example, formed from titanium in aself-aligned siliciding process. In the further insulation structure 34,or in the further insulation structure 34 and the insulation structure31, contact holes are opened to the silicide terminal 29 of the terminalregion 28 and to the gate electrode 33″, and are provided with contacts36 A contact 36 is formed to the silicide terminal 35 of the uppersource/drain region 25.

Although modifications and changes may be suggested by those of ordinaryskill in the art, it is the intention of the inventors to embody withinthe patent warranted hereon all changes and modifications as reasonablyand properly come within the scope of their contribution to the art.

What is claimed is:
 1. A method for the production of a vertical MOStransistor, said method comprising the steps of: forming a mesastructure by applying a semiconductor layer sequence of a lowersource/drain region, a channel region, and an upper source/drain regionto a main surface of a semiconductor substrate and structuring sidewalls of said mesa structure from said semiconductor layer sequence;applying a first auxiliary layer to said semiconductor layer sequence,said first auxiliary layer having sidewalls structured together withsaid semiconductor layer sequence; forming a terminal region for saidlower source/drain region laterally with respect to said mesa structureand in said semiconductor substrate; forming an insulation structurecovering at least said side walls of said lower source/drain region,said step of forming an insulation structure including the steps of:applying an insulating layer having a thickness at least equal to athickness of said semiconductor layer sequence; planarizing saidinsulating layer by chemical/mechanical polishing up to a level of saidfirst auxiliary layer, said first auxiliary layer acting as an etchingstop; and further etching said insulating layer to expose said sidewalls of said channel region; and forming a gate dielectric and a gateelectrode at said side walls of said channel region, said gate electrodehaving a height essentially equal to a height of said channel region. 2.The method according to claim 1, wherein said step of forming a terminalregion further comprises the steps of: covering said side walls of saidmesa structure with a masking spacer; and implanting said semiconductorsubstrate.
 3. The method according to claim 1, wherein the step ofapplying an insulating layer comprises applying said insulating layerwith essentially conformal edge coverage and with a thicknessessentially equal to a thickness of said semiconductor layer sequence;said method further comprising the steps of: applying a second auxiliarylayer to said insulating layer, said second auxiliary layer having asame etching properties and thickness as said first auxiliary layer;structuring said second auxiliary layer to expose said insulating layerat least in a first area laterally overlapping said mesa structure andhaving lateral dimensions greater by twice a thickness of saidinsulating layer than a corresponding lateral dimension of said mesastructure; exposing a surface of said first auxiliary layer bychemical/mechanical polishing said insulating layer; exposing said sidewalls of said channel region by etching said insulating layer, saidfirst auxiliary layer and said second auxiliary layer being an etchingmask; forming a gate dielectric on said side walls of said channelregion; producing a conductive layer to essentially fill up anintermediate space between said insulating layer and said mesastructure; and forming a gate electrode by etching back said conductivelayer.
 4. The method according to claim 3, wherein the step ofstructuring of said second auxiliary layer comprises exposing saidinsulating layer in a second area adjoining said first area; said methodfurther comprising the steps of: during the step of exposing of saidside walls of said channel region, etching said insulating layer in saidsecond area for producing a continuous opening in said first area and insaid second area; filling said continuous opening with said conductivelayer; after the step of forming said gate electrode, providing saidfirst area and said second area with an insulating filling; exposing asurface of said upper source/drain region by selectively removing saidfirst auxiliary layer and said second auxiliary layer with respect tosaid insulating layer and with respect to said insulating filling; andopening a contact hole to said gate electrode in said second area. 5.The method according to claim 4, further comprising the steps of: beforethe step of removing said first auxiliary layer and said secondauxiliary layer, applying a third auxiliary layer, said first auxiliarylayer and said second auxiliary layer being etched selectively withrespect to said third auxiliary layer; and structuring said thirdauxiliary layer for exposing said first auxiliary layer and for coveringsaid second area.
 6. The method according to claim 5, wherein said firstauxiliary layer and said second auxiliary layer comprise siliconnitride; wherein said third auxiliary layer comprises polysilicon;wherein said insulating layer and said insulating filling comprisesilicon oxide; and wherein said conductive layer comprises dopedpolysilicon.
 7. The method according to claim 5, further comprising thestep of: forming a layer of metal silicide on an upper surface of saidterminal region.
 8. The method according to claim 5, further comprisingthe step of: forming a layer of metal silicide on an upper surface ofsaid gate electrode.
 9. The method according to claim 5, furthercomprising the step of: forming a layer of metal silicide on an uppersurface of said upper source/drain region.
 10. The method according toclaim 1, wherein the step of forming an insulation structure includesthe steps of: applying an insulating layer; and structuring saidinsulating layer by chemical/mechanical polishing and etching up to alevel essentially equal to a height of said lower source/drain regionand arranged laterally with respect to said mesa structure; and etchingsaid insulating layer to expose said side walls of said channel region;wherein said step of forming a gate dielectric and a gate electrodeincludes the steps of: forming a gate dielectric at said side walls ofsaid channel region; and forming a gate electrode by depositing andstructuring a conductive layer; and wherein said method furthercomprises the steps of: applying a further insulating layer coveringsaid gate electrode; and forming contacts to said terminal region, saidgate electrode, and said upper source/drain region.
 11. The methodaccording to claim 10, wherein said insulating layer, said furtherinsulating layer, and said insulating filling can comprise siliconoxide; wherein said first auxiliary layer comprises silicon nitride; andwherein said conductive layer comprises doped polysilicon.
 12. Themethod according to claim 11, further comprising the step of: forming alayer of metal silicide on an upper surface of said terminal region. 13.The method according to claim 11, further comprising the step of:forming a layer of metal silicide on an upper surface of said gateelectrode.
 14. The method according to claim 11, further comprising thestep of: forming a layer of metal silicide on an upper surface of saidupper source/drain region.